var annotated_dup =
[
    [ "_", "struct__.html", null ],
    [ "__DMA_HandleTypeDef", "struct_____d_m_a___handle_type_def.html", "struct_____d_m_a___handle_type_def" ],
    [ "__I2C_HandleTypeDef", "struct_____i2_c___handle_type_def.html", "struct_____i2_c___handle_type_def" ],
    [ "__iar_u32", "struct____iar__u32.html", null ],
    [ "__MDMA_HandleTypeDef", "struct_____m_d_m_a___handle_type_def.html", "struct_____m_d_m_a___handle_type_def" ],
    [ "__SPI_HandleTypeDef", "struct_____s_p_i___handle_type_def.html", "struct_____s_p_i___handle_type_def" ],
    [ "__UART_HandleTypeDef", "struct_____u_a_r_t___handle_type_def.html", "struct_____u_a_r_t___handle_type_def" ],
    [ "A_BLOCK_LINK", "struct_a___b_l_o_c_k___l_i_n_k.html", null ],
    [ "ADC_Common_TypeDef", "struct_a_d_c___common___type_def.html", "struct_a_d_c___common___type_def" ],
    [ "ADC_TypeDef", "struct_a_d_c___type_def.html", "struct_a_d_c___type_def" ],
    [ "APSR_Type", "union_a_p_s_r___type.html", "union_a_p_s_r___type" ],
    [ "arm_bilinear_interp_instance_f32", "structarm__bilinear__interp__instance__f32.html", "structarm__bilinear__interp__instance__f32" ],
    [ "arm_bilinear_interp_instance_q15", "structarm__bilinear__interp__instance__q15.html", "structarm__bilinear__interp__instance__q15" ],
    [ "arm_bilinear_interp_instance_q31", "structarm__bilinear__interp__instance__q31.html", "structarm__bilinear__interp__instance__q31" ],
    [ "arm_bilinear_interp_instance_q7", "structarm__bilinear__interp__instance__q7.html", "structarm__bilinear__interp__instance__q7" ],
    [ "arm_biquad_cas_df1_32x64_ins_q31", "structarm__biquad__cas__df1__32x64__ins__q31.html", "structarm__biquad__cas__df1__32x64__ins__q31" ],
    [ "arm_biquad_cascade_df2T_instance_f32", "structarm__biquad__cascade__df2_t__instance__f32.html", "structarm__biquad__cascade__df2_t__instance__f32" ],
    [ "arm_biquad_cascade_df2T_instance_f64", "structarm__biquad__cascade__df2_t__instance__f64.html", "structarm__biquad__cascade__df2_t__instance__f64" ],
    [ "arm_biquad_cascade_stereo_df2T_instance_f32", "structarm__biquad__cascade__stereo__df2_t__instance__f32.html", "structarm__biquad__cascade__stereo__df2_t__instance__f32" ],
    [ "arm_biquad_casd_df1_inst_f32", "structarm__biquad__casd__df1__inst__f32.html", "structarm__biquad__casd__df1__inst__f32" ],
    [ "arm_biquad_casd_df1_inst_q15", "structarm__biquad__casd__df1__inst__q15.html", "structarm__biquad__casd__df1__inst__q15" ],
    [ "arm_biquad_casd_df1_inst_q31", "structarm__biquad__casd__df1__inst__q31.html", "structarm__biquad__casd__df1__inst__q31" ],
    [ "arm_cfft_instance_f32", "structarm__cfft__instance__f32.html", "structarm__cfft__instance__f32" ],
    [ "arm_cfft_instance_f64", "structarm__cfft__instance__f64.html", "structarm__cfft__instance__f64" ],
    [ "arm_cfft_instance_q15", "structarm__cfft__instance__q15.html", "structarm__cfft__instance__q15" ],
    [ "arm_cfft_instance_q31", "structarm__cfft__instance__q31.html", "structarm__cfft__instance__q31" ],
    [ "arm_cfft_radix2_instance_f32", "structarm__cfft__radix2__instance__f32.html", "structarm__cfft__radix2__instance__f32" ],
    [ "arm_cfft_radix2_instance_q15", "structarm__cfft__radix2__instance__q15.html", "structarm__cfft__radix2__instance__q15" ],
    [ "arm_cfft_radix2_instance_q31", "structarm__cfft__radix2__instance__q31.html", "structarm__cfft__radix2__instance__q31" ],
    [ "arm_cfft_radix4_instance_f32", "structarm__cfft__radix4__instance__f32.html", "structarm__cfft__radix4__instance__f32" ],
    [ "arm_cfft_radix4_instance_q15", "structarm__cfft__radix4__instance__q15.html", "structarm__cfft__radix4__instance__q15" ],
    [ "arm_cfft_radix4_instance_q31", "structarm__cfft__radix4__instance__q31.html", "structarm__cfft__radix4__instance__q31" ],
    [ "arm_dct4_instance_f32", "structarm__dct4__instance__f32.html", "structarm__dct4__instance__f32" ],
    [ "arm_dct4_instance_q15", "structarm__dct4__instance__q15.html", "structarm__dct4__instance__q15" ],
    [ "arm_dct4_instance_q31", "structarm__dct4__instance__q31.html", "structarm__dct4__instance__q31" ],
    [ "arm_fir_decimate_instance_f32", "structarm__fir__decimate__instance__f32.html", "structarm__fir__decimate__instance__f32" ],
    [ "arm_fir_decimate_instance_q15", "structarm__fir__decimate__instance__q15.html", "structarm__fir__decimate__instance__q15" ],
    [ "arm_fir_decimate_instance_q31", "structarm__fir__decimate__instance__q31.html", "structarm__fir__decimate__instance__q31" ],
    [ "arm_fir_instance_f32", "structarm__fir__instance__f32.html", "structarm__fir__instance__f32" ],
    [ "arm_fir_instance_f64", "structarm__fir__instance__f64.html", "structarm__fir__instance__f64" ],
    [ "arm_fir_instance_q15", "structarm__fir__instance__q15.html", "structarm__fir__instance__q15" ],
    [ "arm_fir_instance_q31", "structarm__fir__instance__q31.html", "structarm__fir__instance__q31" ],
    [ "arm_fir_instance_q7", "structarm__fir__instance__q7.html", "structarm__fir__instance__q7" ],
    [ "arm_fir_interpolate_instance_f32", "structarm__fir__interpolate__instance__f32.html", "structarm__fir__interpolate__instance__f32" ],
    [ "arm_fir_interpolate_instance_q15", "structarm__fir__interpolate__instance__q15.html", "structarm__fir__interpolate__instance__q15" ],
    [ "arm_fir_interpolate_instance_q31", "structarm__fir__interpolate__instance__q31.html", "structarm__fir__interpolate__instance__q31" ],
    [ "arm_fir_lattice_instance_f32", "structarm__fir__lattice__instance__f32.html", "structarm__fir__lattice__instance__f32" ],
    [ "arm_fir_lattice_instance_q15", "structarm__fir__lattice__instance__q15.html", "structarm__fir__lattice__instance__q15" ],
    [ "arm_fir_lattice_instance_q31", "structarm__fir__lattice__instance__q31.html", "structarm__fir__lattice__instance__q31" ],
    [ "arm_fir_sparse_instance_f32", "structarm__fir__sparse__instance__f32.html", "structarm__fir__sparse__instance__f32" ],
    [ "arm_fir_sparse_instance_q15", "structarm__fir__sparse__instance__q15.html", "structarm__fir__sparse__instance__q15" ],
    [ "arm_fir_sparse_instance_q31", "structarm__fir__sparse__instance__q31.html", "structarm__fir__sparse__instance__q31" ],
    [ "arm_fir_sparse_instance_q7", "structarm__fir__sparse__instance__q7.html", "structarm__fir__sparse__instance__q7" ],
    [ "arm_gaussian_naive_bayes_instance_f32", "structarm__gaussian__naive__bayes__instance__f32.html", "structarm__gaussian__naive__bayes__instance__f32" ],
    [ "arm_iir_lattice_instance_f32", "structarm__iir__lattice__instance__f32.html", "structarm__iir__lattice__instance__f32" ],
    [ "arm_iir_lattice_instance_q15", "structarm__iir__lattice__instance__q15.html", "structarm__iir__lattice__instance__q15" ],
    [ "arm_iir_lattice_instance_q31", "structarm__iir__lattice__instance__q31.html", "structarm__iir__lattice__instance__q31" ],
    [ "arm_linear_interp_instance_f32", "structarm__linear__interp__instance__f32.html", "structarm__linear__interp__instance__f32" ],
    [ "arm_lms_instance_f32", "structarm__lms__instance__f32.html", "structarm__lms__instance__f32" ],
    [ "arm_lms_instance_q15", "structarm__lms__instance__q15.html", "structarm__lms__instance__q15" ],
    [ "arm_lms_instance_q31", "structarm__lms__instance__q31.html", "structarm__lms__instance__q31" ],
    [ "arm_lms_norm_instance_f32", "structarm__lms__norm__instance__f32.html", "structarm__lms__norm__instance__f32" ],
    [ "arm_lms_norm_instance_q15", "structarm__lms__norm__instance__q15.html", "structarm__lms__norm__instance__q15" ],
    [ "arm_lms_norm_instance_q31", "structarm__lms__norm__instance__q31.html", "structarm__lms__norm__instance__q31" ],
    [ "arm_matrix_instance_f32", "structarm__matrix__instance__f32.html", "structarm__matrix__instance__f32" ],
    [ "arm_matrix_instance_f64", "structarm__matrix__instance__f64.html", "structarm__matrix__instance__f64" ],
    [ "arm_matrix_instance_q15", "structarm__matrix__instance__q15.html", "structarm__matrix__instance__q15" ],
    [ "arm_matrix_instance_q31", "structarm__matrix__instance__q31.html", "structarm__matrix__instance__q31" ],
    [ "arm_matrix_instance_q7", "structarm__matrix__instance__q7.html", "structarm__matrix__instance__q7" ],
    [ "arm_merge_sort_instance_f32", "structarm__merge__sort__instance__f32.html", "structarm__merge__sort__instance__f32" ],
    [ "arm_mfcc_instance_f32", "structarm__mfcc__instance__f32.html", "structarm__mfcc__instance__f32" ],
    [ "arm_mfcc_instance_q15", "structarm__mfcc__instance__q15.html", "structarm__mfcc__instance__q15" ],
    [ "arm_mfcc_instance_q31", "structarm__mfcc__instance__q31.html", "structarm__mfcc__instance__q31" ],
    [ "ARM_MPU_Region_t", "struct_a_r_m___m_p_u___region__t.html", "struct_a_r_m___m_p_u___region__t" ],
    [ "arm_pid_instance_f32", "structarm__pid__instance__f32.html", "structarm__pid__instance__f32" ],
    [ "arm_pid_instance_q15", "structarm__pid__instance__q15.html", "structarm__pid__instance__q15" ],
    [ "arm_pid_instance_q31", "structarm__pid__instance__q31.html", "structarm__pid__instance__q31" ],
    [ "arm_rfft_fast_instance_f32", "structarm__rfft__fast__instance__f32.html", "structarm__rfft__fast__instance__f32" ],
    [ "arm_rfft_fast_instance_f64", "structarm__rfft__fast__instance__f64.html", "structarm__rfft__fast__instance__f64" ],
    [ "arm_rfft_instance_f32", "structarm__rfft__instance__f32.html", "structarm__rfft__instance__f32" ],
    [ "arm_rfft_instance_q15", "structarm__rfft__instance__q15.html", "structarm__rfft__instance__q15" ],
    [ "arm_rfft_instance_q31", "structarm__rfft__instance__q31.html", "structarm__rfft__instance__q31" ],
    [ "arm_sort_instance_f32", "structarm__sort__instance__f32.html", "structarm__sort__instance__f32" ],
    [ "arm_spline_instance_f32", "structarm__spline__instance__f32.html", "structarm__spline__instance__f32" ],
    [ "arm_svm_linear_instance_f32", "structarm__svm__linear__instance__f32.html", "structarm__svm__linear__instance__f32" ],
    [ "arm_svm_polynomial_instance_f32", "structarm__svm__polynomial__instance__f32.html", "structarm__svm__polynomial__instance__f32" ],
    [ "arm_svm_rbf_instance_f32", "structarm__svm__rbf__instance__f32.html", "structarm__svm__rbf__instance__f32" ],
    [ "arm_svm_sigmoid_instance_f32", "structarm__svm__sigmoid__instance__f32.html", "structarm__svm__sigmoid__instance__f32" ],
    [ "attitude_t", "structattitude__t.html", null ],
    [ "BDMA_Channel_TypeDef", "struct_b_d_m_a___channel___type_def.html", "struct_b_d_m_a___channel___type_def" ],
    [ "BDMA_TypeDef", "struct_b_d_m_a___type_def.html", "struct_b_d_m_a___type_def" ],
    [ "CallbackTask_t", "struct_callback_task__t.html", null ],
    [ "CAN_Init_Config_s", "struct_c_a_n___init___config__s.html", null ],
    [ "CANComm_Init_Config_s", "struct_c_a_n_comm___init___config__s.html", null ],
    [ "CANCommInstance", "struct_c_a_n_comm_instance.html", null ],
    [ "CEC_TypeDef", "struct_c_e_c___type_def.html", "struct_c_e_c___type_def" ],
    [ "COMP_Common_TypeDef", "struct_c_o_m_p___common___type_def.html", "struct_c_o_m_p___common___type_def" ],
    [ "COMP_TypeDef", "struct_c_o_m_p___type_def.html", "struct_c_o_m_p___type_def" ],
    [ "COMPOPT_TypeDef", "struct_c_o_m_p_o_p_t___type_def.html", "struct_c_o_m_p_o_p_t___type_def" ],
    [ "CONTROL_Type", "union_c_o_n_t_r_o_l___type.html", "union_c_o_n_t_r_o_l___type" ],
    [ "corCoRoutineControlBlock", "structcor_co_routine_control_block.html", null ],
    [ "CORDIC_TypeDef", "struct_c_o_r_d_i_c___type_def.html", "struct_c_o_r_d_i_c___type_def" ],
    [ "CoreDebug_Type", "struct_core_debug___type.html", "struct_core_debug___type" ],
    [ "CRC_TypeDef", "struct_c_r_c___type_def.html", "struct_c_r_c___type_def" ],
    [ "CRS_TypeDef", "struct_c_r_s___type_def.html", "struct_c_r_s___type_def" ],
    [ "DAC_TypeDef", "struct_d_a_c___type_def.html", "struct_d_a_c___type_def" ],
    [ "Daemon_Init_Config_s", "struct_daemon___init___config__s.html", null ],
    [ "daemon_ins", "structdaemon__ins.html", null ],
    [ "DBGMCU_TypeDef", "struct_d_b_g_m_c_u___type_def.html", "struct_d_b_g_m_c_u___type_def" ],
    [ "DCMI_TypeDef", "struct_d_c_m_i___type_def.html", "struct_d_c_m_i___type_def" ],
    [ "DFSDM_Channel_TypeDef", "struct_d_f_s_d_m___channel___type_def.html", "struct_d_f_s_d_m___channel___type_def" ],
    [ "DFSDM_Filter_TypeDef", "struct_d_f_s_d_m___filter___type_def.html", "struct_d_f_s_d_m___filter___type_def" ],
    [ "DJI_Motor_Measure_s", "struct_d_j_i___motor___measure__s.html", null ],
    [ "DJIMotorInstance", "struct_d_j_i_motor_instance.html", null ],
    [ "DLYB_TypeDef", "struct_d_l_y_b___type_def.html", "struct_d_l_y_b___type_def" ],
    [ "DM_Motor_Measure_s", "struct_d_m___motor___measure__s.html", null ],
    [ "DMA2D_TypeDef", "struct_d_m_a2_d___type_def.html", "struct_d_m_a2_d___type_def" ],
    [ "DMA_InitTypeDef", "struct_d_m_a___init_type_def.html", "struct_d_m_a___init_type_def" ],
    [ "DMA_Stream_TypeDef", "struct_d_m_a___stream___type_def.html", "struct_d_m_a___stream___type_def" ],
    [ "DMA_TypeDef", "struct_d_m_a___type_def.html", "struct_d_m_a___type_def" ],
    [ "DMAMUX_Channel_TypeDef", "struct_d_m_a_m_u_x___channel___type_def.html", "struct_d_m_a_m_u_x___channel___type_def" ],
    [ "DMAMUX_ChannelStatus_TypeDef", "struct_d_m_a_m_u_x___channel_status___type_def.html", "struct_d_m_a_m_u_x___channel_status___type_def" ],
    [ "DMAMUX_RequestGen_TypeDef", "struct_d_m_a_m_u_x___request_gen___type_def.html", "struct_d_m_a_m_u_x___request_gen___type_def" ],
    [ "DMAMUX_RequestGenStatus_TypeDef", "struct_d_m_a_m_u_x___request_gen_status___type_def.html", "struct_d_m_a_m_u_x___request_gen_status___type_def" ],
    [ "DMMotor_Send_s", "struct_d_m_motor___send__s.html", null ],
    [ "DMMotorInstance", "struct_d_m_motor_instance.html", null ],
    [ "DTS_TypeDef", "struct_d_t_s___type_def.html", "struct_d_t_s___type_def" ],
    [ "DWT_Time_t", "struct_d_w_t___time__t.html", null ],
    [ "DWT_Type", "struct_d_w_t___type.html", "struct_d_w_t___type" ],
    [ "ETH_TypeDef", "struct_e_t_h___type_def.html", null ],
    [ "EventGroupDef_t", "struct_event_group_def__t.html", null ],
    [ "EXTI_ConfigTypeDef", "struct_e_x_t_i___config_type_def.html", "struct_e_x_t_i___config_type_def" ],
    [ "EXTI_Core_TypeDef", "struct_e_x_t_i___core___type_def.html", "struct_e_x_t_i___core___type_def" ],
    [ "EXTI_HandleTypeDef", "struct_e_x_t_i___handle_type_def.html", "struct_e_x_t_i___handle_type_def" ],
    [ "EXTI_TypeDef", "struct_e_x_t_i___type_def.html", "struct_e_x_t_i___type_def" ],
    [ "FDCAN_ClockCalibrationUnit_TypeDef", "struct_f_d_c_a_n___clock_calibration_unit___type_def.html", "struct_f_d_c_a_n___clock_calibration_unit___type_def" ],
    [ "FDCAN_GlobalTypeDef", "struct_f_d_c_a_n___global_type_def.html", "struct_f_d_c_a_n___global_type_def" ],
    [ "FLASH_CRCInitTypeDef", "struct_f_l_a_s_h___c_r_c_init_type_def.html", "struct_f_l_a_s_h___c_r_c_init_type_def" ],
    [ "FLASH_EraseInitTypeDef", "struct_f_l_a_s_h___erase_init_type_def.html", "struct_f_l_a_s_h___erase_init_type_def" ],
    [ "FLASH_OBProgramInitTypeDef", "struct_f_l_a_s_h___o_b_program_init_type_def.html", "struct_f_l_a_s_h___o_b_program_init_type_def" ],
    [ "FLASH_ProcessTypeDef", "struct_f_l_a_s_h___process_type_def.html", "struct_f_l_a_s_h___process_type_def" ],
    [ "FLASH_TypeDef", "struct_f_l_a_s_h___type_def.html", "struct_f_l_a_s_h___type_def" ],
    [ "FMAC_TypeDef", "struct_f_m_a_c___type_def.html", "struct_f_m_a_c___type_def" ],
    [ "FMC_Bank1_TypeDef", "struct_f_m_c___bank1___type_def.html", "struct_f_m_c___bank1___type_def" ],
    [ "FMC_Bank1E_TypeDef", "struct_f_m_c___bank1_e___type_def.html", "struct_f_m_c___bank1_e___type_def" ],
    [ "FMC_Bank2_TypeDef", "struct_f_m_c___bank2___type_def.html", "struct_f_m_c___bank2___type_def" ],
    [ "FMC_Bank3_TypeDef", "struct_f_m_c___bank3___type_def.html", "struct_f_m_c___bank3___type_def" ],
    [ "FMC_Bank5_6_TypeDef", "struct_f_m_c___bank5__6___type_def.html", "struct_f_m_c___bank5__6___type_def" ],
    [ "FPU_Type", "struct_f_p_u___type.html", "struct_f_p_u___type" ],
    [ "GPIO_Init_Config_s", "struct_g_p_i_o___init___config__s.html", null ],
    [ "GPIO_InitTypeDef", "struct_g_p_i_o___init_type_def.html", "struct_g_p_i_o___init_type_def" ],
    [ "GPIO_TypeDef", "struct_g_p_i_o___type_def.html", "struct_g_p_i_o___type_def" ],
    [ "GPV_TypeDef", "struct_g_p_v___type_def.html", "struct_g_p_v___type_def" ],
    [ "HAL_DMA_MuxRequestGeneratorConfigTypeDef", "struct_h_a_l___d_m_a___mux_request_generator_config_type_def.html", "struct_h_a_l___d_m_a___mux_request_generator_config_type_def" ],
    [ "HAL_DMA_MuxSyncConfigTypeDef", "struct_h_a_l___d_m_a___mux_sync_config_type_def.html", "struct_h_a_l___d_m_a___mux_sync_config_type_def" ],
    [ "HeapRegion", "struct_heap_region.html", null ],
    [ "HSEM_Common_TypeDef", "struct_h_s_e_m___common___type_def.html", "struct_h_s_e_m___common___type_def" ],
    [ "HSEM_TypeDef", "struct_h_s_e_m___type_def.html", "struct_h_s_e_m___type_def" ],
    [ "HTMotor_Measure_t", "struct_h_t_motor___measure__t.html", null ],
    [ "HTMotorInstance", "struct_h_t_motor_instance.html", null ],
    [ "I2C_InitTypeDef", "struct_i2_c___init_type_def.html", "struct_i2_c___init_type_def" ],
    [ "I2C_TypeDef", "struct_i2_c___type_def.html", "struct_i2_c___type_def" ],
    [ "IIC_Init_Config_s", "struct_i_i_c___init___config__s.html", null ],
    [ "iic_temp_s", "structiic__temp__s.html", null ],
    [ "IMU_Data_t", "struct_i_m_u___data__t.html", null ],
    [ "IMU_Param_t", "struct_i_m_u___param__t.html", null ],
    [ "INS_t", "struct_i_n_s__t.html", null ],
    [ "IPSR_Type", "union_i_p_s_r___type.html", "union_i_p_s_r___type" ],
    [ "ITM_Type", "struct_i_t_m___type.html", "struct_i_t_m___type" ],
    [ "IWDG_TypeDef", "struct_i_w_d_g___type_def.html", "struct_i_w_d_g___type_def" ],
    [ "Key_t", "union_key__t.html", null ],
    [ "kf_t", "structkf__t.html", null ],
    [ "LKMotor_Measure_t", "struct_l_k_motor___measure__t.html", null ],
    [ "LKMotorInstance", "struct_l_k_motor_instance.html", null ],
    [ "LL_UTILS_ClkInitTypeDef", "struct_l_l___u_t_i_l_s___clk_init_type_def.html", "struct_l_l___u_t_i_l_s___clk_init_type_def" ],
    [ "LL_UTILS_PLLInitTypeDef", "struct_l_l___u_t_i_l_s___p_l_l_init_type_def.html", "struct_l_l___u_t_i_l_s___p_l_l_init_type_def" ],
    [ "LPTIM_TypeDef", "struct_l_p_t_i_m___type_def.html", "struct_l_p_t_i_m___type_def" ],
    [ "LTDC_Layer_TypeDef", "struct_l_t_d_c___layer___type_def.html", "struct_l_t_d_c___layer___type_def" ],
    [ "LTDC_TypeDef", "struct_l_t_d_c___type_def.html", "struct_l_t_d_c___type_def" ],
    [ "MDIOS_TypeDef", "struct_m_d_i_o_s___type_def.html", null ],
    [ "MDMA_Channel_TypeDef", "struct_m_d_m_a___channel___type_def.html", "struct_m_d_m_a___channel___type_def" ],
    [ "MDMA_InitTypeDef", "struct_m_d_m_a___init_type_def.html", "struct_m_d_m_a___init_type_def" ],
    [ "MDMA_LinkNodeConfTypeDef", "struct_m_d_m_a___link_node_conf_type_def.html", "struct_m_d_m_a___link_node_conf_type_def" ],
    [ "MDMA_LinkNodeTypeDef", "struct_m_d_m_a___link_node_type_def.html", "struct_m_d_m_a___link_node_type_def" ],
    [ "MDMA_TypeDef", "struct_m_d_m_a___type_def.html", "struct_m_d_m_a___type_def" ],
    [ "Motor_Control_Setting_s", "struct_motor___control___setting__s.html", null ],
    [ "Motor_Controller_Init_s", "struct_motor___controller___init__s.html", null ],
    [ "Motor_Controller_s", "struct_motor___controller__s.html", null ],
    [ "Motor_Init_Config_s", "struct_motor___init___config__s.html", null ],
    [ "MPU_Type", "struct_m_p_u___type.html", "struct_m_p_u___type" ],
    [ "NVIC_Type", "struct_n_v_i_c___type.html", "struct_n_v_i_c___type" ],
    [ "OCTOSPI_TypeDef", "struct_o_c_t_o_s_p_i___type_def.html", "struct_o_c_t_o_s_p_i___type_def" ],
    [ "OCTOSPIM_TypeDef", "struct_o_c_t_o_s_p_i_m___type_def.html", "struct_o_c_t_o_s_p_i_m___type_def" ],
    [ "OPAMP_TypeDef", "struct_o_p_a_m_p___type_def.html", "struct_o_p_a_m_p___type_def" ],
    [ "os_mailQ_cb", "structos__mail_q__cb.html", null ],
    [ "os_mailQ_def", "structos__mail_q__def.html", "structos__mail_q__def" ],
    [ "os_messageQ_def", "structos__message_q__def.html", "structos__message_q__def" ],
    [ "os_mutex_def", "structos__mutex__def.html", "structos__mutex__def" ],
    [ "os_pool_cb", "structos__pool__cb.html", null ],
    [ "os_pool_def", "structos__pool__def.html", "structos__pool__def" ],
    [ "os_semaphore_def", "structos__semaphore__def.html", "structos__semaphore__def" ],
    [ "os_thread_def", "structos__thread__def.html", "structos__thread__def" ],
    [ "os_timer_def", "structos__timer__def.html", "structos__timer__def" ],
    [ "osEvent", "structos_event.html", "structos_event" ],
    [ "PID_ErrorHandler_t", "struct_p_i_d___error_handler__t.html", null ],
    [ "PID_Init_Config_s", "struct_p_i_d___init___config__s.html", null ],
    [ "PIDInstance", "struct_p_i_d_instance.html", null ],
    [ "PLL1_ClocksTypeDef", "struct_p_l_l1___clocks_type_def.html", null ],
    [ "PLL2_ClocksTypeDef", "struct_p_l_l2___clocks_type_def.html", null ],
    [ "PLL3_ClocksTypeDef", "struct_p_l_l3___clocks_type_def.html", null ],
    [ "protocol_rm_struct", "structprotocol__rm__struct.html", null ],
    [ "PSSI_TypeDef", "struct_p_s_s_i___type_def.html", "struct_p_s_s_i___type_def" ],
    [ "PWM_Init_Config_s", "struct_p_w_m___init___config__s.html", null ],
    [ "pwm_ins_temp", "structpwm__ins__temp.html", null ],
    [ "PWR_PVDTypeDef", "struct_p_w_r___p_v_d_type_def.html", "struct_p_w_r___p_v_d_type_def" ],
    [ "PWR_TypeDef", "struct_p_w_r___type_def.html", "struct_p_w_r___type_def" ],
    [ "PWREx_AVDTypeDef", "struct_p_w_r_ex___a_v_d_type_def.html", "struct_p_w_r_ex___a_v_d_type_def" ],
    [ "PWREx_WakeupPinTypeDef", "struct_p_w_r_ex___wakeup_pin_type_def.html", "struct_p_w_r_ex___wakeup_pin_type_def" ],
    [ "QEKF_INS_t", "struct_q_e_k_f___i_n_s__t.html", null ],
    [ "QueueDefinition", "struct_queue_definition.html", null ],
    [ "QueuePointers", "struct_queue_pointers.html", null ],
    [ "RAMECC_MonitorTypeDef", "struct_r_a_m_e_c_c___monitor_type_def.html", "struct_r_a_m_e_c_c___monitor_type_def" ],
    [ "RAMECC_TypeDef", "struct_r_a_m_e_c_c___type_def.html", "struct_r_a_m_e_c_c___type_def" ],
    [ "RC_ctrl_t", "struct_r_c__ctrl__t.html", null ],
    [ "rc_ctrl_t", "structrc__ctrl__t.html", null ],
    [ "RCC_ClkInitTypeDef", "struct_r_c_c___clk_init_type_def.html", "struct_r_c_c___clk_init_type_def" ],
    [ "RCC_CRSInitTypeDef", "struct_r_c_c___c_r_s_init_type_def.html", "struct_r_c_c___c_r_s_init_type_def" ],
    [ "RCC_CRSSynchroInfoTypeDef", "struct_r_c_c___c_r_s_synchro_info_type_def.html", "struct_r_c_c___c_r_s_synchro_info_type_def" ],
    [ "RCC_OscInitTypeDef", "struct_r_c_c___osc_init_type_def.html", "struct_r_c_c___osc_init_type_def" ],
    [ "RCC_PeriphCLKInitTypeDef", "struct_r_c_c___periph_c_l_k_init_type_def.html", "struct_r_c_c___periph_c_l_k_init_type_def" ],
    [ "RCC_PLL2InitTypeDef", "struct_r_c_c___p_l_l2_init_type_def.html", "struct_r_c_c___p_l_l2_init_type_def" ],
    [ "RCC_PLL3InitTypeDef", "struct_r_c_c___p_l_l3_init_type_def.html", "struct_r_c_c___p_l_l3_init_type_def" ],
    [ "RCC_PLLInitTypeDef", "struct_r_c_c___p_l_l_init_type_def.html", "struct_r_c_c___p_l_l_init_type_def" ],
    [ "RCC_TypeDef", "struct_r_c_c___type_def.html", "struct_r_c_c___type_def" ],
    [ "remoter_t", "structremoter__t.html", null ],
    [ "RNG_TypeDef", "struct_r_n_g___type_def.html", "struct_r_n_g___type_def" ],
    [ "RTC_TypeDef", "struct_r_t_c___type_def.html", "struct_r_t_c___type_def" ],
    [ "SAI_Block_TypeDef", "struct_s_a_i___block___type_def.html", "struct_s_a_i___block___type_def" ],
    [ "SAI_TypeDef", "struct_s_a_i___type_def.html", "struct_s_a_i___type_def" ],
    [ "SCB_Type", "struct_s_c_b___type.html", "struct_s_c_b___type" ],
    [ "SCnSCB_Type", "struct_s_cn_s_c_b___type.html", "struct_s_cn_s_c_b___type" ],
    [ "SDMMC_TypeDef", "struct_s_d_m_m_c___type_def.html", "struct_s_d_m_m_c___type_def" ],
    [ "SEGGER_BSP_API", "struct_s_e_g_g_e_r___b_s_p___a_p_i.html", null ],
    [ "SEGGER_BUFFER_DESC", "struct_s_e_g_g_e_r___b_u_f_f_e_r___d_e_s_c.html", null ],
    [ "SEGGER_CACHE_CONFIG", "struct_s_e_g_g_e_r___c_a_c_h_e___c_o_n_f_i_g.html", null ],
    [ "SEGGER_PRINTF_API", "struct_s_e_g_g_e_r___p_r_i_n_t_f___a_p_i.html", null ],
    [ "SEGGER_PRINTF_FORMATTER", "struct_s_e_g_g_e_r___p_r_i_n_t_f___f_o_r_m_a_t_t_e_r.html", null ],
    [ "SEGGER_RTT_BUFFER_DOWN", "struct_s_e_g_g_e_r___r_t_t___b_u_f_f_e_r___d_o_w_n.html", null ],
    [ "SEGGER_RTT_BUFFER_UP", "struct_s_e_g_g_e_r___r_t_t___b_u_f_f_e_r___u_p.html", null ],
    [ "SEGGER_RTT_CB", "struct_s_e_g_g_e_r___r_t_t___c_b.html", null ],
    [ "SEGGER_RTT_PRINTF_DESC", "struct_s_e_g_g_e_r___r_t_t___p_r_i_n_t_f___d_e_s_c.html", null ],
    [ "SEGGER_SNPRINTF_CONTEXT_struct", "struct_s_e_g_g_e_r___s_n_p_r_i_n_t_f___c_o_n_t_e_x_t__struct.html", null ],
    [ "SEGGER_SYSVIEW_GLOBALS", "struct_s_e_g_g_e_r___s_y_s_v_i_e_w___g_l_o_b_a_l_s.html", null ],
    [ "SEGGER_SYSVIEW_MODULE_STRUCT", "struct_s_e_g_g_e_r___s_y_s_v_i_e_w___m_o_d_u_l_e___s_t_r_u_c_t.html", null ],
    [ "SEGGER_SYSVIEW_OS_API", "struct_s_e_g_g_e_r___s_y_s_v_i_e_w___o_s___a_p_i.html", null ],
    [ "SEGGER_SYSVIEW_PRINTF_DESC", "struct_s_e_g_g_e_r___s_y_s_v_i_e_w___p_r_i_n_t_f___d_e_s_c.html", null ],
    [ "SEGGER_SYSVIEW_TASKINFO", "struct_s_e_g_g_e_r___s_y_s_v_i_e_w___t_a_s_k_i_n_f_o.html", null ],
    [ "SemaphoreData", "struct_semaphore_data.html", null ],
    [ "Servo_Angle_s", "struct_servo___angle__s.html", null ],
    [ "Servo_Init_Config_s", "struct_servo___init___config__s.html", null ],
    [ "ServoInstance", "struct_servo_instance.html", null ],
    [ "SPDIFRX_TypeDef", "struct_s_p_d_i_f_r_x___type_def.html", "struct_s_p_d_i_f_r_x___type_def" ],
    [ "SPI_Init_Config_s", "struct_s_p_i___init___config__s.html", null ],
    [ "SPI_InitTypeDef", "struct_s_p_i___init_type_def.html", "struct_s_p_i___init_type_def" ],
    [ "spi_ins_temp", "structspi__ins__temp.html", null ],
    [ "SPI_TypeDef", "struct_s_p_i___type_def.html", "struct_s_p_i___type_def" ],
    [ "StreamBufferDef_t", "struct_stream_buffer_def__t.html", null ],
    [ "SWPMI_TypeDef", "struct_s_w_p_m_i___type_def.html", "struct_s_w_p_m_i___type_def" ],
    [ "SYSCFG_TypeDef", "struct_s_y_s_c_f_g___type_def.html", "struct_s_y_s_c_f_g___type_def" ],
    [ "SysTick_Type", "struct_sys_tick___type.html", "struct_sys_tick___type" ],
    [ "SYSVIEW_FREERTOS_TASK_STATUS", "struct_s_y_s_v_i_e_w___f_r_e_e_r_t_o_s___t_a_s_k___s_t_a_t_u_s.html", null ],
    [ "TIM_Base_InitTypeDef", "struct_t_i_m___base___init_type_def.html", "struct_t_i_m___base___init_type_def" ],
    [ "TIM_BreakDeadTimeConfigTypeDef", "struct_t_i_m___break_dead_time_config_type_def.html", "struct_t_i_m___break_dead_time_config_type_def" ],
    [ "TIM_ClearInputConfigTypeDef", "struct_t_i_m___clear_input_config_type_def.html", "struct_t_i_m___clear_input_config_type_def" ],
    [ "TIM_ClockConfigTypeDef", "struct_t_i_m___clock_config_type_def.html", "struct_t_i_m___clock_config_type_def" ],
    [ "TIM_Encoder_InitTypeDef", "struct_t_i_m___encoder___init_type_def.html", "struct_t_i_m___encoder___init_type_def" ],
    [ "TIM_HallSensor_InitTypeDef", "struct_t_i_m___hall_sensor___init_type_def.html", "struct_t_i_m___hall_sensor___init_type_def" ],
    [ "TIM_HandleTypeDef", "struct_t_i_m___handle_type_def.html", "struct_t_i_m___handle_type_def" ],
    [ "TIM_IC_InitTypeDef", "struct_t_i_m___i_c___init_type_def.html", "struct_t_i_m___i_c___init_type_def" ],
    [ "TIM_MasterConfigTypeDef", "struct_t_i_m___master_config_type_def.html", "struct_t_i_m___master_config_type_def" ],
    [ "TIM_OC_InitTypeDef", "struct_t_i_m___o_c___init_type_def.html", "struct_t_i_m___o_c___init_type_def" ],
    [ "TIM_OnePulse_InitTypeDef", "struct_t_i_m___one_pulse___init_type_def.html", "struct_t_i_m___one_pulse___init_type_def" ],
    [ "TIM_SlaveConfigTypeDef", "struct_t_i_m___slave_config_type_def.html", "struct_t_i_m___slave_config_type_def" ],
    [ "TIM_TypeDef", "struct_t_i_m___type_def.html", "struct_t_i_m___type_def" ],
    [ "tmpgpio", "structtmpgpio.html", null ],
    [ "TPI_Type", "struct_t_p_i___type.html", "struct_t_p_i___type" ],
    [ "tskTaskControlBlock", "structtsk_task_control_block.html", null ],
    [ "TTCAN_TypeDef", "struct_t_t_c_a_n___type_def.html", "struct_t_t_c_a_n___type_def" ],
    [ "UART_AdvFeatureInitTypeDef", "struct_u_a_r_t___adv_feature_init_type_def.html", "struct_u_a_r_t___adv_feature_init_type_def" ],
    [ "UART_InitTypeDef", "struct_u_a_r_t___init_type_def.html", "struct_u_a_r_t___init_type_def" ],
    [ "UART_WakeUpTypeDef", "struct_u_a_r_t___wake_up_type_def.html", "struct_u_a_r_t___wake_up_type_def" ],
    [ "USART_Init_Config_s", "struct_u_s_a_r_t___init___config__s.html", null ],
    [ "USART_TypeDef", "struct_u_s_a_r_t___type_def.html", "struct_u_s_a_r_t___type_def" ],
    [ "USARTInstance", "struct_u_s_a_r_t_instance.html", null ],
    [ "USB_Init_Config_s", "struct_u_s_b___init___config__s.html", null ],
    [ "USB_OTG_DeviceTypeDef", "struct_u_s_b___o_t_g___device_type_def.html", "struct_u_s_b___o_t_g___device_type_def" ],
    [ "USB_OTG_GlobalTypeDef", "struct_u_s_b___o_t_g___global_type_def.html", "struct_u_s_b___o_t_g___global_type_def" ],
    [ "USB_OTG_HostChannelTypeDef", "struct_u_s_b___o_t_g___host_channel_type_def.html", "struct_u_s_b___o_t_g___host_channel_type_def" ],
    [ "USB_OTG_HostTypeDef", "struct_u_s_b___o_t_g___host_type_def.html", "struct_u_s_b___o_t_g___host_type_def" ],
    [ "USB_OTG_INEndpointTypeDef", "struct_u_s_b___o_t_g___i_n_endpoint_type_def.html", "struct_u_s_b___o_t_g___i_n_endpoint_type_def" ],
    [ "USB_OTG_OUTEndpointTypeDef", "struct_u_s_b___o_t_g___o_u_t_endpoint_type_def.html", "struct_u_s_b___o_t_g___o_u_t_endpoint_type_def" ],
    [ "Vision_Recv_s", "struct_vision___recv__s.html", null ],
    [ "Vision_Send_s", "struct_vision___send__s.html", null ],
    [ "VREFBUF_TypeDef", "struct_v_r_e_f_b_u_f___type_def.html", "struct_v_r_e_f_b_u_f___type_def" ],
    [ "WWDG_TypeDef", "struct_w_w_d_g___type_def.html", "struct_w_w_d_g___type_def" ],
    [ "xHeapStats", "structx_heap_stats.html", null ],
    [ "xLIST", "structx_l_i_s_t.html", null ],
    [ "xLIST_ITEM", "structx_l_i_s_t___i_t_e_m.html", null ],
    [ "xMEMORY_REGION", "structx_m_e_m_o_r_y___r_e_g_i_o_n.html", null ],
    [ "xMINI_LIST_ITEM", "structx_m_i_n_i___l_i_s_t___i_t_e_m.html", null ],
    [ "xPSR_Type", "unionx_p_s_r___type.html", "unionx_p_s_r___type" ],
    [ "xSTATIC_EVENT_GROUP", "structx_s_t_a_t_i_c___e_v_e_n_t___g_r_o_u_p.html", null ],
    [ "xSTATIC_LIST", "structx_s_t_a_t_i_c___l_i_s_t.html", null ],
    [ "xSTATIC_LIST_ITEM", "structx_s_t_a_t_i_c___l_i_s_t___i_t_e_m.html", null ],
    [ "xSTATIC_MINI_LIST_ITEM", "structx_s_t_a_t_i_c___m_i_n_i___l_i_s_t___i_t_e_m.html", null ],
    [ "xSTATIC_QUEUE", "structx_s_t_a_t_i_c___q_u_e_u_e.html", null ],
    [ "xSTATIC_STREAM_BUFFER", "structx_s_t_a_t_i_c___s_t_r_e_a_m___b_u_f_f_e_r.html", null ],
    [ "xSTATIC_TCB", "structx_s_t_a_t_i_c___t_c_b.html", null ],
    [ "xSTATIC_TIMER", "structx_s_t_a_t_i_c___t_i_m_e_r.html", null ],
    [ "xTASK_PARAMETERS", "structx_t_a_s_k___p_a_r_a_m_e_t_e_r_s.html", null ],
    [ "xTASK_STATUS", "structx_t_a_s_k___s_t_a_t_u_s.html", null ],
    [ "xTIME_OUT", "structx_t_i_m_e___o_u_t.html", null ]
];